Data storage devices and methods for manufacturing the same

ABSTRACT

A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/606,136 filed on May 26, 2017, which claims priority under 35 U.S.C.§ 119 to Korean Patent Application No. 10-2016-0145368, filed on Nov. 2,2016, in the Korean Intellectual Property Office, the disclosure ofwhich is hereby incorporated by reference in its entirety.

BACKGROUND 1. Technical Field

Example embodiments of the inventive concepts relate to semiconductordevices and methods for manufacturing the same, more particularly, todata storage devices and methods for manufacturing the same.

2. Description of Related Art

A spin-transfer torque MTJ (Magnetic Tunnel Junction) element has astacked structure where a nonmagnetic barrier layer (an insulating film)is sandwiched between two ferromagnetic layers, and stores data by achange in a magnetic resistance caused by spin-polarized tunneling. TheMTJ element can be switched into a low resistance state or a highresistance state depending on the magnetization directions of the twoferromagnetic layers. The MTJ element is in a low resistance when themagnetization directions (spin directions) of the two ferromagneticlayers are in a parallel state, and in a high resistance state when themagnetization directions (spin directions) thereof are in ananti-parallel state.

SUMMARY

According to some example embodiments, a method for manufacturing a datastorage device may include: forming a magnetic tunnel junction layer ona substrate; irradiating a first ion beam on the magnetic tunneljunction layer at a first incident angle with respect to a top surfaceof the substrate and in situ in a first chamber to form a plurality ofmagnetic tunnel junction patterns at the magnetic tunnel junction layer,the plurality of magnetic tunnel junction patterns separated from eachother; irradiating a second ion beam on the magnetic tunnel junctionlayer at a second incident angle with respect to the top surface of thesubstrate and in situ in the first chamber, subsequently to irradiatingthe first ion beam on the magnetic tunnel junction layer, the secondincident angle smaller than the first incident angle; and irradiating athird ion beam on the magnetic tunnel junction layer at a third incidentangle with respect to the top surface of the substrate and in situ inthe first chamber, subsequently to irradiating the second ion beam onthe magnetic tunnel junction layer, the third incident angle greaterthan the first incident angle.

According to some example embodiments, a data storage device mayinclude: an interlayer insulating layer on a substrate; a plurality ofcontact plugs in the interlayer insulating layer; a plurality ofmagnetic tunnel junction patterns on the contact plugs; a plurality ofsidewall insulating patterns on sidewalls of the magnetic tunneljunction patterns; and a capping dielectric layer on the plurality ofsidewall insulating patterns, Each magnetic tunnel junction pattern ofthe plurality of magnetic tunnel junction patterns includes a firstmagnetic pattern on the substrate, a tunnel barrier pattern on the firstmagnetic pattern, and a second magnetic pattern on the tunnel barrierpattern. The tunnel barrier pattern may have a thickness varying indirect proportion with proximity to the capping dielectric layer.

According to some example embodiments, a method for manufacturing a datastorage device may include: forming an interlayer insulating layer on asubstrate; forming a magnetic tunnel junction layer on the substrate;irradiating a first ion beam on the magnetic tunnel junction layer toform a plurality of magnetic tunnel junction patterns based on etchingthe magnetic tunnel junction layer, the plurality of magnetic tunneljunction patterns separated from each other; irradiating a second ionbeam on the magnetic tunnel junction layer to remove etch residues fromsidewalls of the magnetic tunnel junction patterns; and irradiating athird ion beam on the magnetic tunnel junction layer to form sidewallinsulating patterns on sidewalls of the magnetic tunnel junctionpatterns based on re-depositing materials separated from the interlayerinsulating layer by the third ion beam on the sidewalls of the magnetictunnel junction patterns.

According to some example embodiments, a method for manufacturing a datastorage device may include: forming an interlayer insulating layer on asubstrate; forming a magnetic tunnel junction layer on the substrate;irradiating a first ion beam on the magnetic tunnel junction layer toform a plurality of magnetic tunnel junction patterns based on etchingthe magnetic tunnel junction layer, the plurality of magnetic tunneljunction patterns separated from each other; and irradiating a secondion beam on the magnetic tunnel junction layer to form sidewallinsulating patterns on sidewalls of the magnetic tunnel junctionpatterns based on re-depositing materials separated from the interlayerinsulating layer by the second ion beam on the sidewalls of the magnetictunnel junction patterns.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIG. 1 is a schematic diagram illustrating an ion beam apparatusaccording to some example embodiments of the inventive concepts.

FIG. 2 is a process flow chart illustrating a method for manufacturing adata storage device according to some example embodiments of theinventive concepts.

FIG. 3 is a plan view illustrating a data storage device according tosome example embodiments of the inventive concepts.

FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, and FIG. 9 are viewsillustrating a method for manufacturing a data storage device accordingto some example embodiments of the inventive concepts, and arecross-sectional views taken along line I-I′ in FIG. 3.

FIG. 10 is an enlarged view of a portion ‘P’ of FIG. 9.

FIG. 11 is a process flow chart illustrating a method for manufacturinga data storage device according to some example embodiments of theinventive concepts.

FIG. 12 is an enlarged view of a data storage device formed according tothe process flow chart of FIG. 11.

FIG. 13 is a view for explaining a magnetic tunnel junction pattern ofFIG. 3.

FIG. 14 is a view for explaining a magnetic tunnel junction pattern ofFIG. 3.

FIG. 15 is a circuit diagram illustrating a unit memory cell of a datastorage device according to some example embodiments of the inventiveconcepts.

FIG. 16 is a diagram illustrating an electronic device 1600 according tosome example embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, example embodiments of the inventive concepts will be fullydescribed with reference to the accompanying drawings.

FIG. 1 is a schematic diagram illustrating an ion beam apparatusaccording to some example embodiments of the inventive concepts.Referring to FIG. 1, an ion beam apparatus 500 may include a chamberassembly 200 in which a process is performed using an ion beam IB, adetector 300 combined with the chamber assembly 200, and a computersystem 400 connected to the chamber assembly 200 and the detector 300.

In some example embodiments, a process performed using an ion beam IBmay include an ion beam etching process, also referred to herein asetching of a material based on directing an ion beam IB on the material,also referred to herein as ion beam IB etching. Ion beam IB etching mayinclude etching the material to form a pattern. The pattern may includean MTJ pattern.

Ion beam IB etching may include directing an ion beam IB into a portionof the chamber assembly 200, also referred to as irradiating at least aportion of the chamber assembly 200 with the ion beam IB, such that theion beam IB is directed on a material held within the portion of thechamber assembly 200. The ion beam IB direct on the material held withinthe portion of the chamber assembly 200 may etch at least a portion ofthe material. Thus, in some example embodiments, an ion beam apparatus500 may be configured to execute ion beam etching with regard to amaterial held within the chamber assembly 200, including executing ionbeam etching of at least a portion of the material.

The chamber assembly 200 may include a source chamber 202 in which aplasma may be generated. In some example embodiments, the chamberassembly 200 is configured to generate an ion beam IB based on thegenerated plasma. The chamber assembly 200 may further include a processchamber 204. The chamber assembly 200 may be configured to perform a inwhich the process is performed using the ion beam IB generated from theplasma in the source chamber 202, including ion beam IB etching of amaterial held within the process chamber 204. The source chamber 202 andthe process chamber 204 may be communicated with each other. The chamberassembly 200 may include a grid 206 therein, and the grid 206 may bebetween the source chamber 202 and the process chamber 204. The grid 206may be configured to control the ion beam IB, such that the grid 206causes the ion beam IB to be irradiated into the process chamber 204. Astage 208 on which a wafer WF may be loaded may be included in theprocess chamber 204. Thus, the stage 208 may be configured to support amaterial, including wafer WF, in the process chamber 204.

As shown in FIG. 1, the stage 208 may be configured to be inclined(“tilted”) with respect to a bottom surface of the chamber assembly 200.The stage 208 is configured to have a tilt angle α with respect to thebottom surface of the chamber assembly 200, so the ion beam IB may beirradiated to the wafer WF at a particular (or, alternatively,predetermined) incident angle β with respect to a top surface of thewafer WF where the incident angle β is a difference between 90 degreesand the tilt angle α. For example, a chuck capable of tilting (e.g.,configured to tilt) in a desired direction may be disposed at a lowerportion of the stage 208 to adjust the tilt angle α.

The incident angle β may be defined by (e.g., may be based on) an angleat which the ion beam IB is irradiated with respect to an upper surfaceof the wafer WF, also referred to as the ion beam IB being directed onthe top surface of the wafer WF. In addition, the incident angle β ofthe ion beam IB may be determined by the tilt angle α of the stage 208.In this specification, the incident angle and the tilt angle may bereferred to as an angle of 90 degrees or less. The ion beam IB may beirradiated to the upper surface of the wafer WF to perform a particular(or, alternatively, predetermined) process on the wafer WF, including anion beam IB etching of at least a portion of the wafer WF. The processmay be performed to form semiconductor devices on the wafer WF. Forexample, the process may be an etch process by which a thin film formedon the wafer WF is etched.

The detector 300 may be configured to detect signals that are generatedfrom a material in the chamber assembly 200 during the process. Such amaterial may include a material formed on the wafer WF, the wafer WFitself, some combination thereof, or the like. The signal may begenerated by the material based on an ion beam IB being directed on thematerial. The computer system 400 may include a controller 402 (alsoreferred to herein as a “processor”) configured to control parameters ofthe chamber assembly 200 using the signals obtained from the detector300, a library 404 (also referred to herein as a “memory”) configured tostore various data, an input/output unit 406 and an interface unit 408.The controller 402 (“processor”) may include a hardware processor suchas central processing unit (CPU), a multi-processor, a distributedprocessing system, an application specific integrated circuit (ASIC),and/or a suitable hardware processing unit, that when, executinginstructions stored in the library 404 (“memory”), configures thecontroller 402 as a special purpose computer to perform the operationsof one or more portions of the ion beam apparatus 500. The library 404may include a hard disk and/or a non-volatile semiconductor memorydevice (e.g., a flash memory device, a phase-change memory device,and/or a magnetic memory device). The controller 402 may be configuredto execute data stored at the library 404 to perform one or moreoperations. The controller 402 may vary at least one of an ion energy,an ion current and the incident angle β of the ion beam IB while theprocess is performed in the process chamber 204. Referring to FIG. 16,the controller 402 may be at least partially implemented by theelectronic device 1600 illustrated in FIG. 16.

FIG. 2 is a process flow chart illustrating a method for manufacturing adata storage device according to some example embodiments of theinventive concepts. FIG. 3 is a plan view illustrating a data storagedevice according to some example embodiments of the inventive concepts.FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, and FIG. 9 are viewsillustrating a method for manufacturing a data storage device accordingto some example embodiments of the inventive concepts, and arecross-sectional views taken along line I-I′ in FIG. 3. In some exampleembodiments, as described herein, a data storage device may include amagnetic memory device (e.g., an MRAM). In some example embodiments, themethods described herein may be at least partially implemented and/orcontrolled by the controller 402 illustrated and described withreference to FIG. 1.

Referring to FIGS. 3 and 4, a first interlayer insulating layer 102 maybe provided (e.g., formed) on a substrate 100. The substrate 100 mayinclude silicon (Si), silicon on insulator (SOI), silicon germanium(SiGe), germanium (Ge) and gallium arsenic (GaAs). Selection elements(not shown) may be provided on the substrate 100, and the firstinterlayer insulating layer 102 may cover the selection elements. Theselection elements may include field effect transistors or diodes. Thefirst interlayer insulating layer 102 may include oxide, nitride,carbide and/or oxynitride. For example, the first interlayer insulatinglayer 102 may include at least one of silicon oxide, silicon nitride,silicon carbide and aluminum oxide.

Contact plugs 104 may be in the first interlayer insulating layer 102.In some example embodiments, the interlayer insulating layer 102surrounds the contact plugs 104. Each of the contact plugs 104 maypenetrate (e.g., extend through) the first interlayer insulating layer102 such that the contact plugs 104 are electrically connected to oneterminal of a corresponding one of the selection elements. The contactplug 104 may include at least one of a doped semiconductor material(e.g., doped silicon), a metal (e.g., tungsten, titanium and/ortantalum), a conducive metal nitride (e.g., titanium nitride, tantalumnitride and/or tungsten nitride), and a metal-semiconductor compound(e.g., metal silicide). In some example embodiments, upper surfaces 104a of the contact plugs 104 may be substantially coplanar with an uppersurface 102 a of the first interlayer insulating layer 102.

As shown in at least FIG. 4, a lower conductive layer 106, a magnetictunnel junction layer 120 and an upper conductive layer 114 may besequentially stacked on the first interlayer insulating layer 102, suchthat the lower conductive layer 106 is on the first interlayerinsulating layer 102, the magnetic tunnel junction layer 120 is on thelower conductive layer 106, and the upper conductive layer 114 is on themagnetic tunnel junction layer 120. The lower conductive layer 106 andthe upper conductive layer 114 may include a conductive metal nitride,such as titanium nitride and/or tantalum nitride. The lower conductivelayer 106 may include a material (e.g., ruthenium (Ru)) that contributesto crystal growth of magnetic layers constituting the magnetic tunneljunction layer 120. The lower conductive layer 106 may be formed by asputtering process, a chemical vapor deposition (CVD) process or anatomic layer deposition (ALD) process. The magnetic tunnel junctionlayer 120 may include a first magnetic layer 108, a tunnel barrier layer110 and a second magnetic layer 112 which are sequentially stacked onthe lower conductive layer 106, such that the first magnetic layer 108is on the lower conductive layer 106, the tunnel barrier layer 110 is onthe first magnetic layer 108, and the second magnetic layer 112 is onthe tunnel barrier layer 110. One magnetic layer of the first and secondmagnetic layers 108 and 112 may correspond to a reference layer that hasa magnetic direction fixed in one direction, and the other magneticlayer of the first and second magnetic layers 108 and 112 may correspondto a free layer that has a magnetic direction changeable to be parallelor anti-parallel to the fixed magnetic direction of the reference layer.

It will be understood that when an element, including a layer, film,region, or substrate is referred to as being “on” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” another element, there are no intervening elements present.

In some example embodiments, the magnetic directions of the referencelayer and the free layer may be substantially perpendicular to aninterface between the tunnel barrier layer 110 and the second magneticlayer 112. In some example embodiments, the magnetic directions of thereference layer and the free layer may be substantially parallel to aninterface between the tunnel barrier layer 110 and the second magneticlayer 112. Hereinafter, the magnetic directions of the reference layerand the free layer will be described in more detail with reference toFIGS. 13 and 14.

The tunnel barrier layer 110 may include at least one of a magnesiumoxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO)layer, a magnesium zinc oxide (MgZnO) layer or a magnesium boron oxide(MgBO) layer. Each of the first magnetic layer 108, the tunnel barrierlayer 110 and the second magnetic layer 112 may be formed by asputtering process, a physical vapor deposition (PVD) process or a CVDprocess. The tunnel barrier layer 110 may be deposited with a firstthickness t1.

Mask patterns may be formed on the magnetic tunnel junction layer 120.The mask patterns may include conductive mask patterns 130 andinsulating mask patterns 135, and the insulating mask patterns 135 maybe disposed on the conductive mask patterns 130. The mask patterns maydefine regions in which pattern structures to be described later will beformed. The conductive mask patterns 130 may include at least one oftungsten, titanium, tantalum, aluminum, or metal nitrides (e.g.,titanium nitride and tantalum nitride). The insulating mask patterns 135may include at least one of silicon oxide, silicon nitride and siliconoxynitride.

Referring to FIGS. 2, 3 and 5, an ion beam IB may be irradiated to themagnetic tunnel junction layer 120 formed on the substrate 100 at afirst incident angle θ₁ in relation to an upper surface 100 a of thesubstrate 100 to form magnetic tunnel junction patterns MTJ separatedfrom each other (S11, hereinafter, referred to as a first step). Themagnetic tunnel junction patterns MTJ may be separated in a firstdirection D1 and in a second direction D2 through a single patterningprocess. Alternatively, a first patterning process for separating themagnetic tunnel junction layer in the first direction D1 and a secondpatterning process for separating the magnetic tunnel junction layer inthe second direction D2 may be sequentially performed. The magnetictunnel junction layer 120 may be etched using the mask patterns 130 and135 as an etch mask. The first step S11 may be performed in the chamberassembly 200 of the ion beam apparatus 500 (e.g., in situ in the chamberassembly 200) described with reference to FIG. 1. In some exampleembodiments, the first step S11 may be performed using the ion beamincluding argon ions (Ar+). The first incident angle θ₁ in relation tothe upper surface 102 a may be determined by the tilt angle of the stage208 described with reference to FIG. 1. For example, the first incidentangle θ₁ may be in the range from about 50 degrees to about 80 degrees.As referred to herein, the ion beam IB that is irradiated to thesubstrate at the first incident angle θ₁ may be referred to as a firstion beam IB.

When the terms “about” or “substantially” are used in this specificationin connection with a numerical value, it is intended that the associatednumerical value include a tolerance of ±10% around the stated numericalvalue. When ranges are specified, the range includes all valuestherebetween such as increments of 0.1%. Moreover, when the words“generally” and “substantially” are used in connection with geometricshapes, it is intended that precision of the geometric shape is notrequired but that latitude for the shape is within the scope of thedisclosure.

Each of the magnetic tunnel junction patterns MTJ may include a firstmagnetic pattern 109, a tunnel barrier pattern 111 and a second magneticpattern 113 which are sequentially stacked on the substrate 100. Thelower conductive layer 106 and the upper conductive layer 114 maycorrespond to lower conductive patterns 107 and upper conductivepatterns 115, respectively. Upper portions of the insulating maskpatterns 135 may be consumed according to the progress of the first stepS11. In the first step S11, the first interlayer insulating layer 102between the magnetic tunnel junction patterns MTJ may be exposed, and anupper portion thereof may be removed to form a recess region RS. In someexample embodiments, after a completion of the first step S11, a level(“height”) of a bottom surface 102 b of the recess region RS may belower than a level of an upper surface 104 a of the contact plug 104 bya first depth h1.

During the first step S11, edge portions 170 of the tunnel barrierpatterns 111 adjacent to the sidewalls 172 of the magnetic tunneljunction patterns MTJ may be thicker than the first thickness t1described with reference to FIG. 4. That is, a thickness of a centralportion 174 of the tunnel barrier pattern 111 between both sidewalls 172of the magnetic tunnel junction pattern MTJ may be maintained at thefirst thickness t1, and a thickness of the edge portion 170 of thetunnel barrier pattern 111 may be a second thickness t2 that is greaterthan the first thickness t1. For example, the thickness of the tunnelbarrier pattern 111 may be gradually increased from the central portion174 to the edge portion 170. A variation of the thickness of the tunnelbarrier pattern 111 may result from oxidation of a portion of the firstand second magnetic patterns 109 and 113 which are adjacent to thetunnel barrier pattern 111 and exposed on the sidewalls 172 of themagnetic tunnel junction pattern MTJ. When the first interlayerinsulating layer 102 is a material containing oxygen, such as siliconoxide, silicon oxynitride and aluminum oxide, oxygen atoms within theinterlayer insulating layer 102 may be moved to the exposed sidewalls172 of the tunnel barrier pattern 111 by the ion beam. Thus, a portionof the first and second magnetic patterns 109 and 113 may be oxidized bythe oxygen atoms. When the first interlayer insulating layer 102 doesnot contain oxygen, the variation of the thickness of the tunnel barrierpattern 111 may not be generated. Hereinafter, example embodiments inwhich the thickness of the tunnel barrier pattern 111 is changed will bedescribed, but the example embodiments are not limited thereto.

Referring to FIGS. 2, 3 and 6, an ion beam IB may be irradiated to thesubstrate 100 having the magnetic tunnel junction patterns MTJ thereonat a second incident angle θ₂ (S12, hereinafter, referred to as a secondstep) in relation to the upper surface 100 a of the substrate. Thesecond incident angle θ₂ may be smaller than the first incident angleθ₁. In some example embodiments, the second incident angle θ₂ may rangefrom about 30 degrees to about 60 degrees. The second step S12 may be aprocess in which etch residues attached to the sidewalls 172 of themagnetic tunnel junction patterns MTJ in the first step S11 are removed.The etch residues may be easily removed from the sidewalls of themagnetic tunnel junction patterns MTJ by irradiating the ion beam with arelatively smaller incident angle than the incident angle of the ionbeam used in the first step S11. The first and second steps S11 and S12may be performed in situ in the same chamber assembly 200. Hereinafter,in this description, “in situ” processing refers to performingsequential processing in the same chamber assembly, with no vacuumbreak. As referred to herein, the ion beam IB that is irradiated to thesubstrate at the second incident angle θ₂ may be referred to as a secondion beam IB.

After completion of the second step S12, the recess region RS may have abottom surface 102 b which is lowered from the upper surface 104 a ofthe contact plug 104 by a second depth h2. The second depth h2 may begreater than the first depth h1. As a result, as shown in M region, aportion of sidewalls 104 b of the contact plug 104 may be exposed. Insome example embodiments, the sidewalls of the contact plug 104 may beexposed in the first step S11, or a third step S13 to be describedlater.

The thickness of the edge portions 170 of the tunnel barrier pattern 111may be a third thickness t3 that is greater than the second thicknesst2. However, the central portion 174 of the tunnel barrier pattern 111may be maintained at the first thickness t1. A portion of the sidewalls172 of the magnetic tunnel junction pattern MTJ may be etched togetherwith the etch residues in the second step S12. As a result, as shown inFIG. 6, the magnetic tunnel junction pattern MTJ may have a reducedwidth in a lower portion thereof. Although the insulating mask pattern135 is further consumed during the second step S12, at least a portionof the insulating mask pattern 135 may remain on the conductive maskpattern 130 after completion of the second step S12.

Referring to FIGS. 2, 3 and 7, an ion beam IB may be irradiated to thesubstrate 100 having the magnetic tunnel junction patterns MTJ thereonat a third incident angle θ₃ (S13, hereinafter, referred to as a thirdstep). As referred to herein, the ion beam IB that is irradiated to thesubstrate at the third incident angle θ₃ may be referred to as a thirdion beam IB. The third incident angle θ₃ may be greater than the firstincident angle θ₁ in relation to upper surface 100 a of the substrate.In some example embodiments, the third incident angle θ₃ may range fromabout 70 degrees to about 90 degrees. The third step S13 may becontinuously performed along with the first and second steps S11 and S12in the same chamber assembly. That is, the first to third steps S11, S12and S13 may be performed in situ.

In some example embodiments, step S12 as shown in FIGS. 2, 3, and 6 maybe omitted, such that the third ion beam IB that is irradiated at thethird incident angle θ₃ may be referred to as a second ion beam IB thatis irradiated at a second incident angle.

Since the ion beam in the third step S13 is irradiated at the relativelyhigh incident angle with respect to the upper surface 100 a of thesubstrate 100, the first interlayer insulating layer 102 may be moreaffected by the ion beam than the sidewalls 172 of the magnetic tunneljunction pattern MTJ. As a result, amount of materials to be separatedfrom the first interlayer insulating layer 102 by the ion beam may bemore than that in first step and second steps S11 and S12, and some ofthem may be re-deposited 180 on the sidewalls 172 of the magnetic tunneljunction pattern MTJ to form sidewall insulating patterns 141. Thesidewall insulating patterns 141 may include the same materials as thefirst interlayer insulating layer 102. For example, the sidewallinsulating patterns 141 may include at least one of silicon oxide,silicon nitride, silicon carbide and aluminum oxide.

When an ion incident energy in the third step S13 is greater than an ionincident energy in the first step S11, an excessive over-etch withrespect to the magnetic tunnel junction pattern MTJ may be generated,and when the ion incident energy in the third step S13 is smaller thanan ion incident energy in the second step S12, the sidewall insulatingpatterns 141 may be not formed. Thus, the ion incident energy in thethird step S13 may be greater than the ion incident energy in the secondstep S12, and may be smaller than the ion incident energy in the firststep S11. The ion incident energy in the first to third steps S11, S12and S13 may be compared by measuring a voltage of the grid 206 describedwith reference to FIG. 1.

The insulating mask pattern 135 may be further consumed during the thirdstep S13. After completion of the third step S13, the insulating maskpattern 135 may be completely consumed. Alternatively, even after thecompletion of the third step S13, a portion of the insulating maskpattern 135 may remain on the conductive mask pattern 130. After thecompletion of the third step S13, the bottom surface 102 b of the recessregion RS may be lowered from the upper surface of the contact plug 104by a third depth h3 that is greater than the second depth h2. Thethickness of the edge portion 170 of the tunnel barrier pattern 111 maybe a fourth thickness t4 that is greater than the third thickness t3.However, the thickness of the central portion 174 of the tunnel barrierpattern 111 may be maintained at the first thickness t1. Accordingly,the tunnel barrier pattern 111 may have a thickness varying in directproportion with proximity to the sidewalls 172.

Referring to FIGS. 2, 3 and 8, a capping dielectric layer 145 may beformed on a resultant structure in which the sidewall insulatingpatterns 141 are formed (S14, a fourth step). A formation of the cappingdielectric layer 145 may be performed in a different chamber assemblyfrom the chamber assembly in which the first to third steps S11, S12 andS13 are performed. That is, after the completion of the third step S13,the wafer WF may be taken out of the chamber assembly 200 described withreference to FIG. 2 (e.g., a first chamber), and the capping dielectriclayer 145 may be formed after being transferred to another chamber(e.g., a second chamber).

When the wafer is moved between chambers or equipment, externalmaterials, such as oxygen, nitrogen or water (H₂O) may penetrate intothe magnetic tunnel junction pattern MTJ, and thus, the data storagedevice may be deteriorated. According to some example embodiments of theinventive concepts, before moving the wafer WF to form the cappingdielectric layer 145, the sidewall insulating patterns 141 may be formedto prevent such deterioration. As a result, the reliability and/orperformance of MTJs that may be included in a manufactured data storagedevice may be improved by being protected from such deterioration. Thus,data storage devices having improved reliability and/or performance maybe manufactured, thereby at least partially mitigating a problem ofreduced data storage device performance and/or reliability as a resultof magnetic tunnel junction pattern MTJ deterioration as a result ofexternal materials penetrating in the magnetic tunnel junction patternMTJ when the wafer WF is moved between chambers or equipment duringmanufacture of the data storage device.

A method of forming the sidewall insulating patterns 141 in the thirdstep S13 may include oxidizing conductive residues attached to thesidewalls of the magnetic tunnel junction pattern MTJ in the previousstep. Since the sidewall insulating patterns 141 are formed using thefirst interlayer insulating layer 102 located relatively below as sourcematerial, an amount of the material re-deposited on the mask patterns130 and 135 may be small as compared with general deposition methods. Asa result, a subsequent contact hole process or planarization process canproceed more efficiently. In addition, since the sidewall insulatingpatterns 141 are formed using an in situ process without an additionalapparatus or supply of additional source material, the process can besimplified.

The capping dielectric layer 145 may be formed by a CVD process or a PVDprocess. In some example embodiments, the capping dielectric layer 145may include silicon oxide, silicon nitride or silicon oxynitride. Thecapping dielectric layer 145 may be conformally formed on the magnetictunnel junction patterns MTJ and the upper surface 102 a of the firstinterlayer insulating layer 102 (the upper surface of the firstinterlayer insulating layer 102 including the bottom surface 102 b ofthe recess region RS).

A second interlayer insulating layer 150 may be formed on the cappingdielectric layer 145 (S15, a fifth step). The second interlayerinsulating layer 150 may be formed to fill spaces between the magnetictunnel junction patterns MTJ. For example, the second interlayerinsulating layer 150 may include silicon oxide or silicon oxynitride.

Referring to FIGS. 3 and 9, conductive lines 160 may be formed afterperforming a planarization process to expose upper surfaces 130 a of theconductive mask patterns 130. The conductive mask pattern 130 may beconfigured to function as a top electrode TE. The conductive line 160may include metal and/or conductive metal nitride.

Referring to FIGS. 2 and 16, in some example embodiments, an electronicdevice may be manufactured based on the manufactured data storage device(S16, a sixth step). In some example embodiments, where the electronicdevice (e.g., electronic device 1600 as shown in FIG. 16) includes amemory, the manufacture of the electronic device may includemanufacturing a memory that incorporates a data storage devicemanufactured according to one or more example embodiments as describedherein and further incorporating the memory into the manufacturedelectronic device.

FIG. 10 is an enlarged view of a portion ‘P’ of FIG. 9. FIG. 13 is aview for explaining an example of a magnetic tunnel junction pattern ofFIG. 3. FIG. 14 is a view for explaining another example of a magnetictunnel junction pattern of FIG. 3. Hereinafter, a data storage deviceaccording to some example embodiments of the inventive concepts will bedescribed in more detail with reference to FIGS. 3, 9, 10, 13 and 14.

Referring to FIGS. 3, 9 and 10, the interlayer insulating layer 102 maybe provided on the substrate 100. Select elements (not shown) may beprovided on the substrate 100, and the interlayer insulating layer 102may cover the select elements. The select elements may include fieldeffect transistors or diodes. Contact plugs 104 may be provided in thefirst interlayer insulating layer 102. Each of the contact plugs 104 maypenetrate the first interlayer insulating layer 102 so as to beelectrically connected to one terminal of a corresponding one of theselection elements. In some example embodiments, a recess region RS maybe provided on an upper portion of the first interlayer insulating layer102, and a level of a bottom surface 102 b of the recess region RS maybe lower than a level of an upper surface 104 a of the contact plug 104.The lower conductive pattern 107, the magnetic tunnel junction patternMTJ and the upper conductive pattern 115 may be sequentially disposed onthe contact plug 104. The upper conductive pattern 115 may be omitted.

The magnetic tunnel junction pattern MTJ may include the first magneticpattern 109, the second magnetic pattern 113 and the tunnel barrierpattern 111 interposed therebetween. Sidewall insulating patterns 141may be provided on the sidewalls 172 of the magnetic tunnel junctionpattern MTJ. The sidewall insulating patterns 141 may include the samematerial as the first interlayer insulating layer 102. For example, thesidewall insulating pattern 141 may include at least one of siliconoxide, silicon nitride, silicon carbide and aluminum oxide. A cappingdielectric layer 145 may be provided on the sidewall insulating patterns141. For example, the capping dielectric layer 145 may include siliconoxide, silicon nitride or silicon oxynitride. The capping dielectriclayer 145 may be conformally formed on the magnetic tunnel junctionpatterns MTJ and the upper surface 102 a of the first interlayerinsulating layer 102. A second interlayer insulating layer 150 may beformed on the capping dielectric layer 145.

A thickness of a central portion 174 of the tunnel barrier pattern 111between both sidewalls 172 of the magnetic tunnel junction pattern MTJmay be the first thickness t1, and a thickness of the edge portion 170of the tunnel barrier pattern may be a fourth thickness t4 that isgreater than the first thickness t1. For example, the thickness of thetunnel barrier pattern 111 may be gradually increased toward the cappingdielectric layer 145. Due to this shape of the tunnel barrier pattern111, a leakage current of the data storage device may be reduced.Accordingly, the tunnel barrier pattern 111 may have a thickness varyingin direct proportion with proximity to the capping dielectric layer 145.

At a portion adjacent to the tunnel barrier pattern 111, the sidewallinsulating pattern 141 may have a fifth thickness t5 and the cappingdielectric layer 145 may have a sixth thickness t6. The sixth thicknesst6 may be greater than the fifth thickness t5.

In some example embodiments, referring to FIG. 13, magnetizationdirections 109 a and 113 a of the first and second magnetic patterns 109and 113 may be substantially parallel to an interface between the tunnelbarrier pattern 111 and the second magnetic pattern 113. In FIG. 13, thefirst magnetic pattern 109 may be a reference pattern, and the secondmagnetic pattern 113 may be a free pattern. However, the inventiveconcepts are not limited thereto. Alternatively, the first magneticpattern 109 may be the free pattern, and the second magnetic pattern 113may be the reference pattern. The first and second magnetic patterns 109and 113 having the magnetic directions 109 a and 113 a, which areparallel to the interface between the tunnel barrier pattern 111 and thesecond magnetic pattern 113, may include ferromagnetic materials. Thefirst magnetic pattern 109 corresponding to the reference pattern mayfurther include an anti-ferromagnetic material used to fix amagnetization direction of the ferromagnetic material included in thefirst magnetic pattern 109.

In some example embodiments, referring to FIG. 14, magnetizationdirections 109 b and 113 b of the first and second magnetic patterns 109and 113 may be substantially perpendicular to an interface between thetunnel barrier pattern 111 and the second magnetic pattern 113. In FIG.14, the first magnetic pattern 109 may be a reference pattern, and thesecond magnetic pattern 113 may be a free pattern. However, theinventive concepts are not limited thereto. Alternatively, the firstmagnetic pattern 109 may be the free pattern, and the second magneticpattern 113 may be the reference pattern. The first and second magneticpatterns 109 and 113 having the magnetic directions 109 b and 113 b,which are perpendicular to the interface between the tunnel barrierpattern 111 and the second magnetic pattern 113, may include at leastone of a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, orCoFeDy), a perpendicular magnetic material having a L1_(o) structure,CoPt having a hexagonal closed packed lattice (HCP) crystal structure,or a perpendicular magnetic structure. The perpendicular magneticmaterial having a L1_(o) structure may include at least one of FePthaving the L1_(o) structure, FePd having the L1_(o) structure, CoPdhaving the L1_(o) structure, or CoPt having the L1_(o) structure. Theperpendicular magnetic structure may include magnetic layers andnon-magnetic layers which are alternately and repeatedly stacked. Forexample, the perpendicular magnetic structure may include at least oneof (Co/Pt)n, (CoFe/Pt)n, (CoFe/Pd)n, (Co/Pd)n, (Co/Ni)n, (CoNi/Pt)n,(CoCr/Pt)n, or (CoCr/Pd)n, where “n” denotes the number of bilayers.

Referring back to FIGS. 3 and 9, conductive lines 160 may be provided onthe second interlayer insulating layer 150. The conductive lines 160 mayserve as bit lines. When viewed in a plan view, the conductive line 160may extend in a first direction D1, and may be electrically connected tothe magnetic tunnel junction patterns MTJ arranged along the firstdirection D1. Each of the magnetic tunnel junction patterns MTJ may beelectrically connected to the conductive line 160 through the topelectrode TE which is corresponding to each of the magnetic tunneljunction patterns MTJ. When viewed in a plan view, the plurality ofconductive lines 160 may be arranged in a second direction D2intersecting the first direction D1.

FIG. 11 is a process flow chart illustrating a method for manufacturinga data storage device according to some example embodiments of theinventive concepts. FIG. 12 is an enlarged view of a data storage deviceformed according to the process flow chart of FIG. 11. The samedescription of the overlapping parts will be omitted for the sake ofsimplicity.

The process flow chart in FIG. 11 may be substantially the same as theprocess flow chart in FIG. 2 except for an oxygen treatment process S12a performed between the second step S12 and the third step S13. Theoxygen treatment S12 a may be performed by supplying oxygen ions oroxygen molecules into the chamber assembly 200 of FIG. 1. For example,the oxygen ions may be supplied into the process chamber 204 of FIG. 1in the form of an ion beam. After completion of the first and secondsteps S11 and S12, conductive materials remaining on the sidewalls ofthe magnetic tunnel junction pattern MTJ may be oxidized by the oxygentreatment process 512 a. Thus, as shown in FIG. 12, an inner insulatingpattern 149 may be formed on the sidewalls 172 of the magnetic tunneljunction pattern MTJ before the sidewall insulating pattern 141 isformed by the oxygen treatment process 512 a. The inner insulatingpattern 149 may include metal oxide or metal oxynitride. The innerinsulating pattern 149 may have a thinner thickness than the thicknessof the sidewall insulating pattern 141.

FIG. 15 is a circuit diagram illustrating a unit memory cell of a datastorage device according to some example embodiments of the inventiveconcepts.

Referring to FIG. 15, the data storage device to some exampleembodiments of the inventive concepts may be a magnetic memory device.The unit memory cell MC may include a memory element ME and a selectelement SE. The memory element ME may be provided between a bit line BLand a word line WL, and the select element SE may be provided betweenthe memory element ME and the word line WL. The memory element ME may bea variable resistance device whose resistance can be switched to one oftwo states by an electric pulse applied thereto. In some exampleembodiments, the memory element ME may be formed to have a layeredstructure whose electric resistance can be changed by a spin transferprocess using an electric current passing therethrough. For example, thememory element ME may have a layered structure configured to exhibit amagnetoresistance property, and may include at least one ferromagneticmaterial and/or at least one antiferromagnetic material. The selectelement SE may be configured to selectively control a flow of electriccharge passing through the memory element ME. For example, the selectelement SE may be one of a diode, a p-n-p bipolar transistor, an n-p-nbipolar transistor, an n-channel metal-oxide-semiconductor field effecttransistor (NMOSFET) and a p-channel metal-oxide-semiconductor fieldeffect transistor (PMOSFET). When the select element SE is a threeterminal switching device, such as a bipolar transistor or a MOSFET, anadditional interconnection line may be connected to the select elementSE.

The memory element ME may include a first magnetic structure MS1, asecond magnetic structure MS2 and a tunnel barrier TBR interposedtherebetween. The first magnetic structure MS1, the second magneticstructure MS2 and the tunnel barrier TBR may constitute a magnetictunnel junction pattern MTJ. The first and second magnetic structuresMS1 and MS2 may respectively include at least one magnetic layer that isformed of a magnetic material. The memory element ME may further includea bottom electrode BE and a top electrode. The bottom electrode may beinterposed between the second magnetic structure MS2 and the selectelement SE. The top electrode TE may be interposed between the firstmagnetic structure MS1 and the bit line BL.

FIG. 16 is a diagram illustrating an electronic device 1600 according tosome example embodiments.

Referring to FIG. 16, the electronic device 1600 includes a memory 1620,a processor 1630, and a communication interface 1640.

The electronic device 1600 may be included in one or more variouselectronic devices. In some example embodiments, the electronic device1600 may include a computing device. A computing device may include apersonal computer (PC), a tablet computer, a laptop computer, a netbook,some combination thereof, or the like. The memory 1620, the processor1630, and the communication interface 1640 may communicate with oneanother through a bus 1610.

In some example embodiments, the memory 1620 may include one or more ofthe data storage devices that may be manufactured according to any ofthe methods as described herein.

The communication interface 1640 may communicate data from an externaldevice using various Internet protocols. The external device mayinclude, for example, a computing device.

The processor 1630 may execute a program and control the electronicdevice 1600. A program code to be executed by the processor 1630 may bestored in the memory 1620. An electronic system may be connected to anexternal device through an input/output device (not shown) and exchangedata with the external device.

The memory 1620 may store information. The memory 1620 may be a volatileor a nonvolatile memory. The memory may be a magnetic memory device(e.g., an MRAM). The memory 1620 may be a non-transitory computerreadable storage medium. The memory may store computer-readableinstructions that, when executed, cause the execution of one or moremethods, functions, processes, etc. as described herein. In some exampleembodiments, the processor 1630 may execute one or more of thecomputer-readable instructions stored at the memory 1620.

In some example embodiments, the communication interface 1640 mayinclude a USB and/or HDMI interface. In some example embodiments, thecommunication interface 1850 may include a wireless communicationinterface.

In some example embodiments, the electronic device 1600 may at leastpartially comprise the controller 402 illustrated and described withreference to FIG. 1. As such, the electronic device 1600, in someexample embodiments, may be configured to perform any of themanufacturing methods that may be controlled by the controller 402.

While the inventive concepts have been described with reference to someexample embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirits and scopes of the inventive concepts. Therefore, itshould be understood that the above embodiments are not limiting, butillustrative. Thus, the scopes of the inventive concepts are to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing description.

What is claimed is:
 1. A device comprising: a substrate; a firstinterlayer insulating layer disposed on the substrate; a contact plugdisposed in the first interlayer insulating layer; a magnetic tunneljunction layer disposed on the contact plug; and a sidewall insulatingpattern disposed on a sidewall of the magnetic tunnel junction layer,wherein the magnetic tunnel junction pattern includes a first magneticlayer, a tunnel barrier layer disposed on the first magnetic layer, anda second magnetic layer disposed on the tunnel barrier layer, and athickness of an edge portion of the tunnel barrier layer is greater thana thickness of a center portion of the tunnel barrier layer.
 2. Thedevice of claim 1, further comprising a capping layer disposed on thefirst interlayer insulating layer and on the sidewall insulatingpattern.
 3. The device of claim 1, further comprising: a lowerconductive layer disposed between the conductive plug and the firstmagnetic layer; and an upper conductive layer disposed on the secondmagnetic layer.
 4. The device of claim 3, further comprising: a masklayer disposed on the upper conductive layer; a second interlayerinsulating layer disposed on the capping layer; and a conductive linedisposed on the second interlayer insulating layer.
 5. The device ofclaim 1, wherein the contact plug penetrates the first interlayerinsulating layer.
 6. The device of claim 1, wherein the tunnel barrierlayer includes at least one of a magnesium oxide (MgO) layer, a titaniumoxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium zinc oxide(MgZnO) layer and a magnesium boron oxide (MgBO) layer.
 7. The device ofclaim 1, wherein the sidewall insulating pattern includes at least oneof silicon oxide, silicon nitride, silicon carbide and aluminum oxide.8. The device of claim 1, wherein the capping layer includes siliconoxide, silicon nitride or silicon oxynitride.
 9. The device of claim 1,wherein a thickness of a middle portion of the sidewall insulatingpattern is greater than a thickness of an upper portion of the sidewallinsulating pattern, and greater than a thickness of a lower portion ofthe sidewall insulating pattern.
 10. The device of claim 1, wherein afirst surface of the sidewall insulating pattern includes a point atwhich a slope of the first surface of the sidewall insulating patternchanges.
 11. A data storage device comprising: a substrate; aninterlayer insulating layer disposed on the substrate; a contact plugdisposed in the interlayer insulating layer; a magnetic tunnel junctionlayer disposed on the contact plug; and a sidewall insulating patterndisposed on a sidewall of the magnetic tunnel junction layer, whereinthe magnetic tunnel junction pattern includes a first magnetic layer, atunnel barrier layer disposed on the first magnetic layer, and a secondmagnetic layer disposed on the tunnel barrier layer, a thickness of anedge portion of the tunnel barrier layer is greater than a thickness ofa center portion of the tunnel barrier layer, and a first surface of thesidewall insulating pattern includes a point at which a slope of thefirst surface of the sidewall insulating pattern changes.
 12. The datastorage device of claim 11, wherein a lower portion of the sidewallinsulating pattern contacts a sidewall of the contact plug.
 13. The datastorage device of claim 11, further comprising a capping layer disposedon the interlayer insulating layer and on the sidewall insulatingpattern, wherein a thickness of the capping layer is greater than athickness of the sidewall insulating pattern.
 14. The data storagedevice of claim 13, wherein a first surface of the capping layerincludes a point at which a slope of the first surface of the cappinglayer changes.
 15. The data storage device of claim 11, furthercomprising a conductive pattern disposed on the second magnetic layer,wherein a width of the tunnel barrier layer is greater than a width ofthe conductive pattern.
 16. The data storage device of claim 11, whereina thickness of the sidewall insulating pattern is not uniform.
 17. Anelectronic device comprising: a substrate; a first interlayer insulatinglayer disposed on the substrate; a contact plug disposed in the firstinterlayer insulating layer; a magnetic tunnel junction layer disposedon the contact plug, and including a first magnetic layer, a tunnelbarrier layer disposed on the first magnetic layer and a second magneticlayer disposed on the tunnel barrier layer; a sidewall insulatingpattern disposed on a sidewall of the magnetic tunnel junction layer; acapping layer disposed on the interlayer insulating layer and on thesidewall insulating pattern; and a second interlayer insulating layerdisposed on the capping layer, wherein a thickness of an edge portion ofthe tunnel barrier layer is greater than a thickness of a center portionof the tunnel barrier layer, and a thickness of a middle portion of thesidewall insulating pattern is greater than a thickness of an upperportion of the sidewall insulating pattern, and greater than a thicknessof a lower portion of the sidewall insulating pattern.
 18. Theelectronic device of claim 17, wherein a first surface of the sidewallinsulating pattern includes a point at which a slope of the firstsurface of the sidewall insulating pattern changes.
 19. The electronicdevice of claim 17, wherein a first surface of the capping layerincludes a point at which a slope of the first surface of the cappinglayer changes.
 20. The electronic device of claim 17, wherein athickness of the capping layer is greater than a thickness of thesidewall insulating pattern.